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PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis, &I2C Control
Features
* * * * * * * * * * * * Up to 5.0Gbps PCI Express Gen-2 Serial Re-driver Supporting 8 differential channels or 4 lanes of PCIe Interface I2C configuration controls (3.3V Tolerant) Adjustable receiver equalization and transmitter de-emphasis and output levels Variable input an output termination 1:2 channel broadcast Channel loop-back Electrical Idle fully supported Receiver detect and individual output control Single supply voltage, 1.2V 0.05V Power down modes Packaging: 56-contact TQFN, Pb-free & Green
Description
Pericom Semiconductor's PI2EQX5864 is a low power, PCI-express compliant signal re-driver. The device provides programmable equalization, amplification, and de-emphasis by using 8 select bits, to optimize performance over a variety of physical mediums by reducing Inter-symbol interference. PI2EQX5864 supports eight 100-Ohm Differential CML data I/O's between the Protocol ASIC to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user's platform. The integrated equalization circuitry provides flexibility with signal integrity of the PCI-express signal before the re-driver, whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the signal after the re-driver. In addition to providing signal re-conditioning, Pericom's PI2EQX5864 also provides power management Stand-by mode operated by a Bus Enable pin.
Block Diagram
+ - xyRx+ xyRx+ - + xxTx+ xxTxInput level detect to control logic Output Controls
Pin Configuration
SDA PRSNT2# RXD_A GND GND RES_A# SCL VDD
Equalizer
+ - Output Controls A B Input level detect to control logic + -
-
xyTx+ xyTx-
Equalizer
+ -
VDD A0RX+ A0RXB0TX+ B0TXVDD A1RX+ A1RXB1TX+ B1TXVDD A2RX+ A2RXB2TX+ B2TXVDD A3RX+ A3RXB3TX+ B3TX-
xyRx+ xyRx-
56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 9 10 11 12 13 14 15 16 17 18 19 20 41 40 39 38 37 36 35 34 33 32 31
A0TX+ A0TXB0RX+ B0RXVDD A1TX+ A1TXB1RX+ B1RXVDD A2TX+ A2TXB2RX+ B2RXVDD A3TX+ A3TXB3RX+ B3RXVDD
Data Lane Repeats 4 Times
Mode
Control registers & logic Power Management
SDA SCL
LB# RXD_x RES_x
30 29 21 22 23 24 25 26 27 28 VDD RXD_B MODE RES_B# A0 A1 LB#
I2C Control
Ax
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Pin Description Pin # Data Signals 2 3 48 47 7 8 43 42 12 13 38 47 17 18 33 32 46 45 4 5 41 40 9 10 36 35 14 15 31 30 19 20 Control Signals 26, 27, 25 28 Pin Name A0RX+, A0RXA0TX+, A0TXA1RX+, A1RXA1TX+, A1TXA2RX+, A2RXA2TX+, A2TXA3RX+, A3RXA3TX+, A3TXB0RX+, B0RXB0TX+, B0TXB1RX+, B1RXB1TX+, B1TXB2RX+, B2RXB2TX+, B2TXB3RX+, B3RXB3TX+, B3TXA0, A1, A4 LB# Type I I O O I I O O I I O O I I O O I I O O I I O O I I O O I I O O I I Description CML inputs for Channel A0, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. CML outputs for Channel A0, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise. CML inputs for Channel A1, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. CML outputs for Channel A1, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise. CML inputs for Channel A2, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. CML outputs for Channel A2, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise. CML inputs for Channel A3 with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. CML outputs for Channel A3, with internal 50-Ohm pull up during normal operation and and 2K-Ohm pull up otherwise. CML inputs for Channel B0, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. CML outputs for Channel B0, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise. CML inputs for Channel B1, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. CML outputs for Channel B1, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise. CML inputs for Channel B2, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. CML outputs for Channel B2, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise. CML inputs for Channel B3, with internal 50-Ohm pull down during normal operation, and >200K-Ohm otherwise. CML outputs for Channel B3, with internal 50-Ohm pull up during normal operation and 2K-Ohm pull up otherwise. I2C programmable address bit A0, A1 and A4. Loopback control input. Input with innernal 100K-Ohm oull-up resistor. LB# = High or open for normal operation. LB# = Low for loopback connection of A_RX to A_TX and B_TX. Enables I2C control when LOW. Has internal 100K-Ohm pull-up resistor. A LVCMOS high level selects input pins control, and disables I2C operation. Note, during startup, input status of the control pin (LB#, RES_A/B#, RXD_A/B) will be latched to set the initial register state. Input with internal 100K-Ohm pull-up resistor, card present is an active low signal to indicate the existence of a receiver, and will enable all channels, need to tie low for normal operation. (Continued on Next Page)
23
Mode
I
51
PRSNT2#
I
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54 RES_A# I RES_A# is an active low channel reset input for Channel A0, A1, A2 and A3 with internal 100K-Ohm pull-up resistor. When low, receiver detection cycle is reset, and normal detection cycle is carry on after the pin goes high. RES_B# is an active low channel reset input for Channel B0, B1, B2 and B3 with internal 100K-Ohm pull-up resistor. When low, receiver detection cycle is reset, and normal detection cycle is carry on after the pin goes high. Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100KOhm pull-up resistor. Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100KOhm pull-up resistor. I2C SCL clock input. Up to 3.3V input tolerance. I2C SDA data input. Up to 3.3V input tolerance Supply Ground 1.2V Supply Voltage
24
RES_B#
I
50 22 53 52 55, 56, Center Pad 1, 6, 11, 16, 21, 29, 34, 39, 44, 49
RXD_A RXD_B SCL SDA GND VDD
I I I/O I/O PWR PWR
DESCRIPTION of OPERATION
Configuration Modes Device configuration can be performed in two ways depending on the state of the MODE input. MODE determines whether IC configuration status is from the input pins or via I2C control. When MODE is set high, the configuration input pins set the configuration operating state as stored in configuration registers. While MODE is set high, changes to these control registers are disabled and the initial condition is protected from any changes to insuring a known operating state. When the MODE pin is low, reprogramming of these control registers via I2C is allowed. Note that the MODE pin is not latched, and is always active to enable or disable I2C access. During initial power-on, the value at the configuration input pins: LB#, RES_A#, RES_B#,RXD_A and RXD_B, will be latched to the configuration registers as initial startup states. Equalizer Configuration The PI2EQX5864 input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) resulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-frequency signal components. Because either too little, or too much, signal compensation may be non-optimal eight levels are provided to adjust for any application. Equalizer configuration can be programmed via I2C when the mode pin is low. Each group of four channels, A and B, has separate equalization control, and all four channels within the group are assigned the same configuration state. The Equalizer Selection table below describes the register state and associated operation of the equalizer. Equalizer Selection SEL2_[A:B] 0 0 0 0 1 1 1 1
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SEL1_[A:B] 0 0 1 1 0 0 1 1
SEL0_[A:B] 0 1 0 1 0 1 0 1
3
@1.25GHz 0.5dB 0.6dB 1.0dB 1.9dB 2.8dB 3.6dB 5.0dB 7.7dB
@2.5GHz 1.2dB 1.5dB 2.6dB 4.3dB 5.8dB 7.1dB 9.0dB 12.3dB
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The PI2EQX5864 provides flexible output strength and emphasis controls to provide the optimum signal to pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean with good eye opening. Control of output configuration is grouped for the A and B channels, so that each channel within the group has the same setting. Output configuration can be set via I2C when the mode pin is LOW. The Output Swing Control table shows available configuration settings for output level control, as specified by the SELx_y registers.
Output Swing Control
S1_[A:B] 0 0 1 1 S0_[A:B] 0 1 0 1 Swing (Diff. VPP) 1V 0.5V 0.7V 0.9V
Emphasis settings are determined by the state of the Dx_y input pins and configuration registers, as shown below. De-Emphasis is selected as the default power-on mode in following the PCI Express specification, but can be changed to Pre-emphasis via reprogramming the Loopback and Emphasis Control register using the I2C interface.
Output De-emphasis Adjustment
D2_[A:B] 0 0 0 0 1 1 1 1 D1_[A:B] 0 0 1 1 0 0 1 1 D0_[A:B] 0 1 0 1 0 1 0 1 De-emphasis 0dB -2.5dB -3.5dB -4.5dB -5.5dB -6.5dB -7.5dB -8.5dB
Input Level Detect
An input level detect and output squelch function is provided on each channel to eliminate re-transmission of input noise. A continuous signal level below the Vth- threshold causes the output driver to go to a high-impredance state, so that both the positive and negative output signal are pulled to VDD by the internal pull-up resistors. This feature supports L0S PCI Express Electrical Idle state.
Card Present Function
The PRSNT2# input allows direct control of the number of active lanes using the PRSNT2# signal from a PCI Express connector or cable. PRSNT2# is a level sensitive input pin, and controls both directions of the receiver detect function. The receiver detect state machine is only active when PRSNT2# is low, otherwise, the input termination will be high-impedance and output termination will be 2K-Ohm. See the I/O operation table for more information.
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Receiver Detect Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load device on the output, the channel can be automatically enabled for operation. This allows the PI2EQX5864 to configure itself properly depending on the devices it is communicating with, whether it is a 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card. Receiver Detect is enabled by the RXD_A, or RXD_B pins, or alternatively via I2C programming. When RXD_A or RXD_B is set to low, the Receiver Detect operation for that group of channels is disabled, and those channels go directly to 50-Ohm input termination to ground and 50-Ohm output termination to Vdd (for a valid differential channel input level) or to 2K-Ohm (if the signal level is less than the threshold level). The RES_A#, and RES_B# inputs are used to reset the receiver detect state machine to its initial state. RES_A# and RES_B# control the received detect reset for the A and B group of channels respectively. The start of the receiver detect cycle starts when RES_A# or RES_B# transitions from low to high. When a Receiver Detect cycle begins the differential channel pins are enabled with a 2K-Ohm pullup to Vdd. A 50-Ohm Receiver termination will change the pin level. This pin level is evaluated after a fixed time-out, and the channel is then set into the proper operating state. The register bits RX50_Ax and RX50_Bx represent the receiver detect result for their specific channels. The I/O operation table summarizes the relationships and operation of receiver detect and other signals involved with I/O control.
I/O Operation Control
Control Inputs PD# 0 1 PRSNT2# RXD_x RES_x# X X X 1 X X Detection States RX50 SIG_x X X X X Data Channel I/O Input Termination Output Termination Mode Hi-Z Hi-Z Full IC power down, all channels disabled Hi-Z Hi-Z No receiver (defined by PRSNT2#), all channels disabled Hi-Z 2K-Ohm pull-up Channel disabled, output pulls to Vdd. Receiver detect reset 50-Ohm pull2K-Ohm pull-up Channel enabled, no input down signal, output pulls to Vdd. Receiver detect disabled 50-Ohm pull50-Ohm pull-up Channel enabled, valid input down signal detected, output driving. Receiver detect disabled. Hi-Z 2K-Ohm pull-up Channel disabled. Receiver detect reset. Hi-Z 2K-Ohm pull-up Channel disabled, output pulls to Vdd. Receiver detect enabled, no receiver detected. 50-Ohm pull2K-Ohm pull-up Channel inactive, output pulls down to Vdd. Receiver detect enabled, receiver detected. No input signal 50-Ohm pull50-Ohm pull-up Channel active, valid input down signal detected, output driving. Receiver detect enabled, load detected.
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0
0
0
X
X
1
0
0
1
X
0
1
0
0
1
X
1
1 1
0 0
1 1
0 1
X 0
X X
1
0
1
1
1
0
1
0
1
1
1
1
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Loopback Operation
Each lane of the 5864 provides a loopback mode for test purposes which is controlled by a strapping pin and I2C register bit. The LB# pin controls all lanes together. When this pin is high normal data mode is enabled. When LB# is low the loopback mode is enabled. The figure below diagrams this operation. Loopback is not intended to be dynamically switched, and the normal system application is to initialize to one configuration or the other. The Loopback mode can also support mux/demux operation. Using I2C configuration, unused inputs and outputs can be disabled to minimize power and unnecessary noise.
A0 B0
A0
A0 B0
A0
B0
B0
Normal Operation LB#=0
Loopback Mode LB#=1
A0 B0
A0
A0 B0
A0
B0
B0
Mux Function ODIS_AO = 1 Solid: LB_A0B0#=1 Dashed: LB_A0B0#=0
Demux Function INDIS_BO = 1 Solid: LB=0 Dashed: LB=1
Loopback Modes I2C Operation
The 5806 I2C controller operates as a slave device, supporting standard rate operation of 100Kbps, with 7-bit addressing mode, with support for offset byte-write and read. The data byte format is 8 bit bytes. The bytes must be accessed in sequential order from the lowest to the highest byte with the ability to stop after any complete byte has been transferred. Address bits A4, A1 and A0 are programmable to support multiple chips environment. The data is loaded until a Stop sequence is issued. Note that the I2C inputs, SCL and SDA operate at 1.2V logic levels and are 3.3V tolerant.
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Configuration Register Summary
Byte 0 1 2 3 4 5 6 7 8 9 10 11 Mnemonic SIG RX50 LBEC INDIS OUTDIS RESET PWR RXDE AEOC BEOC RSVD RSVD Function Signal Detect, indicates valid input signal level Receiver Detect Output, indicates whether a receiver load was detected Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (preemphasis or de-emphasis) Channel Input Disable, controls whether s channels input buffer is enabled or disabled Channel Output Disable: Controls whether a channels output buffer is enabled or disabled Channel Reset Power Down Control, enables power down for each channel individually Receiver Detect Enable, controls the receiver detect operation A-Channels Equalizer and Output Control B-Channels Equalizer and Output Control Reserved Reserved
Register Description
Byte 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Bit Name Type Power-on State
7 SIG_A0 R X
6 SIG_B0 R X
5 SIG_A1 R X
4 SIG_B1 R X
3 SIG_A2 R X
2 SIG_B2 R X
1 SIG_A3 R X
0 SIG_B3 R X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level Threshold Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-level noise or electrical idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the input level is above Vth-, then SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
Byte 1 - Receiver Detect Output Register (RX50)
RX50_xy = 1 = load detected, RX50_xy = 0 = No reciever found
Bit Name Type Power-on State
7 RX50_A0 R X
6 RX50_B0 R X
5 RX50_A1 R X
4 RX50_B1 R X
3 RX50_A2 R X
2 RX50_B2 R X
1 RX50_A3 R X
0 RX50_B3 R X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device. RX50_xy is at a logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was not detected. The RX50 register is read-only, and is undefined after power-up until a Receiver Detection cycle completes.
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Byte 2 - Loopback and Emphasis Control Register (LBEC)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit Name Type Power-on State
7 LB_A0B0# R/W LB#
6 LB_A1B1# R/W LB#
5 LB_A2B2# R/W LB#
4 LB_A3B3# R/W LB#
3 DE_A R/W 1
2 DE_B R/W 1
1 rsvd R X
0 rsvd R X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
Individual control for each lane is provided for the loopback function via this register.
BYTE 3 - Channel Input Disable (INDIS)
INDIS_xy=0=enable input, INDIS_xy=1=disable input
Bit Name
7 INDIS_A0
6 INDIS_B0
5 INDIS_A1
4 INDIS_B1
3 INDIS_A2
2 INDIS_B2
1 INDIS_A3 R/W 0
0 INDIS_ B3 R/W 0
Type R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 State Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Input Disable register, provides control over the input buffer of each channel independently. When and INDIS_xy bit is logic 1, then the input buffer is switched off and the input termination is high impedance. This feature can be used for PCB testing, and when only one input is used during Loopback as a demux function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode).
BYTE 4 - Channel Output Disable (OUTDIS)
ODIS_xy=0=enable output, ODIS_xy=1=disable output
Bit Name
7 ODIS_A0
6 ODIS_B0
5 ODIS_A1
4 ODIS_B1
3 ODIS_A2
2 ODIS_B2
1 ODIS_ A3 R/W 0
0 ODIS_ B3 R/W 0
Type R/W R/W R/W R/W R/W R/W Power-on 0 0 0 0 0 0 State Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Output Disable register, allows control over the output buffer of each channel independently. When and OUTDIS_xy bit is logic 1, then the output buffer is switched off and the termination is high impedance. This feature can be used for PCB testing, and when only one output is used during Loopback as a mux function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode).
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control BYTE 5 - Channel Reset (RESET)
RES_xy# =0=reset, RES_xy# =1=normal operation. Latch from RES_A# & RES_B# inputs at startup
Bit Name
7 RES_A0#
6 RES_B0#
5 RES_A1#
4 RES_B1#
3 RES_A2#
2 RES_B2#
1 RES_A3# R/W 1
0 RES_B3# R/W 1
Type R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 Power-on State Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition from 0 to 1 initiates a new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled). While static at 0 or 1, the RES_zy# bit will have no effect on operation. The Channel Reset bits are read/write allowing the current state to be checked.
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Bit Name Type Power-on State
7 PD_A0# R/W 1
6 PD_B0# R/W 1
5 PD_A1# R/W 1
4 PD_B1# R/W 1
3 PD_A2# R/W 1
2 PD_B2# R/W 1
1 PD_A3# R/W 1
0 PD_B3# R/W 1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Power Down Control register allows for individual control over each channel for power savings. When PD_xy# is logic 0 the channel is turned off. When PD_xy# is 1 then the channel is enabled for normal operation.
BYTE 7 - Receiver Detect Enable (RXD)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Bit Name Type Power-on State
7 RXD_A0 R/W 1
6 RXD_B0 R/W 1
5 RXD_A1 R/W 1
4 RXD_B1 R/W 1
3 RXD_A2 R/W 1
2 RXD_B2 R/W 1
1 RXD_A3 R/W 1
0 RXD_B3 R/W 1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual channel. When RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1, then the receiver detect state machine is enabled for operation. The initial state of the register bits are determined by the RXD_A and RXD_B input pins during power-up.
BYTE 8 - A-Channels Equalizer and Output Control (AEOC)
SELx_A: Equalizer configuration, Dx_A: Emphasis control, Sx_A: Output level control (see Configuration Table)
Bit Name Type Power-on State
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7 SEL0_A R/W 1
6 SEL1_A R/W 1
5 SEL2_A R/W 1
4 D0_A R/W 1
3 D1_A R/W 1
2 D2_A R/W 1
1 S0_A R/W 1
0 S1_A R/W 1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use 9
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control
The A-Channels Equalizer and Output Control register is used to control the configuration of the input equalizer and output emphasis and levels of the four A channels. These register bits are loaded from the input configuration pins of the same name at power-on. These bits may be changed if the MODE# input is set to allow I2C configuration. Please refer to the tables (1) Equalizer Configuration, (2) Output Swing Configuration and (3) Output Emphasis Configuration earlier in this document for setting information. All four A channels get the same configuration settings.
BYTE 9 - B-Channels Equalizer and Output Control (BEOC)
SELx_B: Equalizer configuration, Dx_B: Emphasis control, Sx_B: Output level control (see Configuration Table)
Bit Name Type Power-on State
7 SEL0_B R/W 1
6 SEL1_B R/W 1
5 SEL2_B R/W 1
4 D0_B R/W 1
3 D1_B R/W 1
2 D2_B R/W 1
1 S0_B R/W 1
0 S1_B R/W 1
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The B-Channels Equalizer and Output Control register is used to control the configuration of the input equalizer and output emphasis and levels of the four B channels. These register bits are loaded from the input configuration pins of the same name at power-on. These bits may be changed if the MODE# input is set to allow I2C configuration. Please refer to the tables (1) Equalizer Configuration, (2) Output Swing Configuration and (3) Output Emphasis Configuration earlier in this document for setting information. All four B channels get the same configuration settings.
BYTE 10 - Reserved BYTE 11 - Reserved
Reserved Bytes 10 and 11 are also visible via the I2C interface. These bytes are R/W, are initialized to 0 at power up, are used for IC manufacturing test purposes and should not be changed for normal operation. Start & Stop Conditions A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition, as shown in the figure below.
I2C
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1. Read sequence
ACK PI2EQX5864
PI2EQX5864 DATA OUT ACK
ACK
DATA OUT N
NO ACK
I2C Master start DEV SEL R/W stop
2. Write sequence
ACK PI2EQX5864 ACK ACK ACK ACK
I2C Master start DEV SEL DUMMY BYTE DATA IN 1 stop R/W DATA IN N
3. Combined sequence
ACK DUMMY BYTE ACK
PI2EQX5864
ACK DATA OUT 1 ACK
ACK DATA OUT N NO ACK
I2C Master
start
start
DEV SEL R / W
DEV SEL R / W
Notes: 1. only block read and block write from the lowest byte are supported for this application. 2. for some I2C application, an offset address byte will be presented at the second byte in write command, which is called dummy byte here and will be simply ignored in this application for correct interoperation.
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature...................................... -65C to +150C Supply Voltage to Ground Potential........ -0.5V to +2.5V DC SIG Voltage....................................... -0.5V to VDD +0.5V Current Output ........................................ -25mA to +25mA Power Dissipation Continuous ............... 1W Operating Temperature............................ 0 to +70C AC/DC Electrical Characteristics Power Supply Characteristics (VDD = 1.2 0.05V, TA = 0 TO 70C) Symbol Parameter Conditions IDDactive Power supply current All channels switching - active IDDstandby Power supply current PD_xy# all 0 - standby Power supply current IDD-channel - per channel, Active AC Performance Characteristics (VDD = 1.2 0.05V, TA = 0 TO 70C) Symbol Parameter Conditions Channel latency from Tpd input to output
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Min.
Typ. Max. Units 800 mA 5 50 10. mA mA
Min.
Typ. 750
Max. Units ps
CML Receiver Input (VDD = 1.2 0.05V, TA = 0 TO 70C) Symbol Parameter Conditions ZRX-DIFFDC Differential Input DC Impedance ZRX-DC DC Input Impedance VRX-DIFFPP VRX-CMACP VthDifferential Input Peak-to-peak Voltage AC Peak Common Mode Input Voltage Signal detect threshold voltage
Min. 80 40 0.175
Typ. Max. Units 100 120 Ohms 50 60 Ohms
1.200 V 150 100 150 mV mV
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Equalizer Symbol JRS-T JRS-D JRM Parameter Residual jitter Residual jitter Random jitter Conditions Total Deterministic Note 2 Min. Typ. Max. 0.3 0.2 Units Ulp-p Ulp-p psrms
1.5
Notes 1. K28.7 pattern is applied differentially at point A as shown in AC test circuit (see figure). 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 x RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of the AC test circuit (see figure).
CML Transmitter Output (VDD = 1.2V 0.05V, TA = 0 to 70C) Symbol Parameter Conditions Output resistance Single ended ZOUT ZTX-DIFF-DC VDIFFP VTX-DIFFP-P VTX-C tF, tR CTX(1) DC Differential TX Impedance Output Voltage Swing, Differential Differential Peak-topeak Ouput Voltage Common-Mode Voltage
Min. 40 80
Typ. 50 100
Max. 60 120 1000 2.0
Units Ohms Ohms mVpp V V
|VTX-D+ - VTX-D-|
200
VTX-DIFFP-P = 2 * | VTX- 0.4 D+ - VTX-D- | | VTX-D+ + VTX-D- | / 2
VDD0.3 150 200
Transition Time 20% to 80% (3) AC Coupling Capacitor
75
ps nF
Notes: 1. Recommended external coupling capacitor.
Digital I/O DC Specifications (VDD = 1.2V 0.05V, TA = 0 to 70C) Symbol Parameter Conditions Min. DC input logic high VDD/2 VIH +0.2 VIL DC input logic low -0.3 VOH VOL Vhys IIH(1) IIL1(2) IIL2(3) DC output logic high DC output logic low Hysteresis of Schmitt trigger input Input high current Input low current Input low current IOH = 4mA IOL = 4mA 0.2 VDD0.4
Typ.
Max. Units VDD+0.3 V VDD/2 -0.2 V V 0.4 V V 250 uA uA uA
-250 -500
Notes: 1. Includes input signals A1, A2, A4, LB#, MODE#, PRSNT2#, RES_[A:B]#, RXD_[A:B], SCL, SDA 2. For control inputs without pullups: A1, A2, A4, SCL, SDA 3. Control inputs with pull-ups include: LB#, MODE#, PRSNT2#, RES_[A:B]#, RXD_[A:B]
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control
SDA and SCL I/O for I2C-bus (VDD = 1.2 0.05v, TA = 0 to 70C) Symbol VIH VIL VOL Vhys Parameter DC input logic high DC input logic low DC output logic low Hysteresis of Schmitt trigger input Conditions Min. 1.1 -0.3 IOL = 3mA 0.2 Typ. 3.6 0.7 0.4 Max. V V V V Units
Characteristics of the SDA and SCL bus lines for F/S-mode I2C-bus devices(1) Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb Parameter SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Buss free time between a STOP and STOP condition Capacitive load for each bus line Conditions Min. 0 4.0 4.7 4.0 4.7 5.0 250 - 4.0 4.7 - Typ. Max. 100 - - - - - - 100 300 - - 400 Unit kHz s s s s s ns ns ns s s pF
Notes: 1. All values referred to VIHmin and VILmax levels. 2. A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control
START
STOP
START
SDA tf SCL tHD;STA tHD;DAT t SU;STA t SU;STO tLOW tSU;DAT tf tr tBUF
t HD;STA
S
HIGH
Sr
P
S
I2C Timing
Channel Latency, 5.0 Gbps
Figure 10 - Equalizer Response Characteristics
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PS8934A
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control
Output Level Settings (1V left, and 0.5V right at 5.0 Gbps)
0.0 dB (Dx = 000)
-3.5 dB (Dx = 010)
-6.5 dB (Dx = 101)
-8.5 dB (Dx = 111)
Output De-emphasis Characteristics
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PS8934A
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control
Eye Diagrams 5.0Gbps (input left, output right)
Data Waveforms, 2.5Gbps (left) & 5.0Gbps (right)
FR4
Signal Source A B
D.U.T.
C
SmA Connector 30IN
SmA Connector
In
Out
AC Test Circuit Referenced in the Electrical Characteristic Table
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PS8934A
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PI2EQX5864 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis and I2C Control Packaging Mechanical: 56-Contact TQFN (ZF)
DATE: 03/03/06
DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN) PACKAGE CODE: ZF56 DOCUMENT CONTROL #: PD-2024 REVISION: B
Ordering Information Ordering Number PI2EQX5864ZFE
Package Code ZF
Package Description Pb-free & Green 56-Contact TQFN
Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free and Green * X suffix = Tape/Reel
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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PS8934A
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